Apparatus and method for generating a distributed clock signal using gear ratio techniques

ABSTRACT

The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.

[0001] This application claims priority to the provisional patentapplication entitled, “Gear Ratio Techniques and Distributed ClockGeneration”, Serial No. 60/062,035, filed on Oct. 10, 1997.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to electronic circuits and thefield of distributed clock circuits. More particularly, the presentinvention relates to a method and circuit for synchronizing clocksignals from separate clock domains with minimized latency.

[0004] 2. Description of the Related Art

[0005] The demands created by today's high-speed electronic equipmenthave generated a number of problems for circuit designers andmanufacturers. For example, many applications require that twosubsystems running at different frequencies communicate with each other.Generally, logic running at a given clock frequency is said to beoperating in a clock domain.

[0006] This synchronization problem has been previously addressed eitherby eliminating one of the clock domains or by adding synchronizationlogic. Unfortunately, the synchronization logic adds unwanted latencydue to the additional circuitry. Moreover, the disparity between theclock domains may include different frequencies and/or phases, furthercomplicating the synchronization circuit design and adding to thelatency. Alternatively, eliminating one of the clock domains is notalways feasible because there are practical limitations as to how manycomponents a single clock source may support. Also a single clock domainwill limit the independent optimization of each subsystem.

[0007] An example of a system with two clock domains is a memorysubsystem that contains a memory clock domain and a controller clockdomain. As stated above, the simplest solution to the clock domainproblem is to ensure that a system only has one clock domain.

[0008]FIG. 1 shows a prior art system that contains only one clockdomain. A clock source CLKSOURCE 102 uses a crystal 104 to generate ahigh-frequency clock, BUSCLK 106. In this example, BUSCLK 106 is showntraveling past a controller CTRL_A 108 to a termination resistor 110.The use of terminated transmission lines is common place in high-speedclock distribution, but is not required for this discussion.

[0009] In FIG. 1, BUSCLK 106 is buffered by buffers 112, insidecontroller 108. The use of buffers is common practice, but not required.Finally, the buffered version of BUSCLK 106 drives a clock divider C 114which divides BUSCLK 106 to generate a clock called SYNCLK 116. Thedivider could have any value, including one (i.e., SYNCLK=BUSCLK).

[0010] A key aspect of FIG. 1 is that all of the logic in controller 108runs off the same SYNCLK 116. SYNCLK 116 is buffered by buffers 117 andoutput from the controller 108 to drive the rest of the system as thesystem clock, SCLK_A 118. Since all of the control logic and the entiresystem run off a clock derived from SYNCLK 116, there are no clockdomains to cross and no asynchronous data transfers required. However,it is very restrictive to require an entire system to run off one clockdomain, and this approach is not practical for most systems. Forexample, running the system using one clock signal will result in eachsubsystem not being optimized to its fullest potential. Hence, eachsubsystem will, instead, be restricted by the limitations posed by adifferent subsystem.

[0011]FIG. 2 illustrates a more common approach. Elements appearing inFIG. 2, which were introduced in FIG. 1, are referred to with the samereference numerals which were originally used. In FIG. 2, CLKSOURCE 102generates BUSCLK 106, which is divided to generate SYNCLK 116. However,in FIG. 2 a separate clock source MAIN CLK SRC 208 generates a secondclock, SCLK_B 210, which is used by the rest of the system. SCLK_B 210is buffered by buffers 211 to generate PCLK_B 212, inside CTRL_B 214.Alternately, SCLK_B 210 could be divided or multiplied to generatePCLK_B 212. After the clocks are generated, there are two clock domains,that of PCLK_B 212 and that of SYNCLK 116, between which data needs tobe exchanged.

[0012] Because PCLK_B 212 and SYNCLK 116 are asynchronous, data cannotbe exchanged directly from logic running in one clock domain to logicrunning in the other clock domain without losing data. Instead, dataneeds to be synchronized as it is passed between the two clock domains.For example, in FIG. 2, FIFOs 216 are shown which are driven by bothPCLK_B 212 and SYNCLK 116 to synchronize data that is transferredbetween the domain of PCLK_B 212 and the domain of SYNCLK 116. Whilethis synchronization is effective in solving some of the clock domaincrossing problems, it adds additional latency to the data transfer.

[0013] For example, when two clock domains are asynchronous (nofrequency or phase relationship), blocks of information are typicallytransferred with dual port memories. Data is written into a memory fromone clock domain and read from the memory by the other clock domain. Asecond memory is needed for communication in the reverse direction.Control signals coordinate these empty-fill operations. The controlsignals are often double-sampled with registers in each clock domain toavoid metastability problems. This solution is robust, but typically hasa significant latency cost because of the synchronization delay.Additionally, it can have a bandwidth cost if the empty-fill operationscan not be overlapped because of synchronization overhead.

[0014] In view of the foregoing, it would be highly desirable tosynchronize clocks from different clock domains, for example in a memorysystem, while minimizing any latency caused by the additionalsynchronization circuitry.

SUMMARY OF THE INVENTION

[0015] The present invention provides a method and apparatus forsynchronizing signal transfers between two clock domains, where theclock domains have a gear ratio relationship. A gear ratio means thatthe clocks are related by a ratio, such that each clock has a differentinteger number of clock cycles in a common period. Also, in addition toa gear ratio relationship, the clocks may have a synchronized edge atthe end of the common period. For each clock, the cycles in the commonperiod are “colored”, i.e., identified by a number (1st, 2nd, etc.). Byusing the coloring technique, the appropriate clock edge to perform adata or control signal transfer can be identified. The edges arepreferably chosen to minimize the latency of the transfer.

[0016] In one embodiment, after a clock edge of the faster clockstrobing the data into a buffer, the appropriate clock edge of theslower clock to strobe out the data is the next rising clock edge of theslower clock in the common period. This relationship results in onlysome of the fast clock edges being used for strobing data in, but all ofthe slow clock edges being used for strobing data out.

[0017] Conversely, for data transfers from the slow clock domain to thefast clock domain, the invention preferably uses the latest fast clockrising edge after a slow clock rising edge strobing in the data from theslow clock domain, but before the next slow clock rising edge strobingin the next data. Although the next fast clock edge could be used, sincethere are more fast clock edges than are needed for maximum slow clockbandwidth, the latest clock is chosen to maximize the data setup time.

[0018] The invention can be applied to different clock ratios byappropriately varying the color code (number of cycles in the commonperiod) and by varying which color value is used for the strobing. Thus,by simply programming registers, for example, with new color values andnew selected color values for transfers, the same physical hardware canaccommodate many different gear ratio clocks.

[0019] In yet another embodiment, the present invention provides amethod and apparatus for a distributed clock generation loop whichgenerates clock signals that allow asynchronous data transfers betweendifferent clock domains with minimized latency. This aspect is helpful,in part, because even if two clocks are related by a gear ratio, thereis no inherent phase relationship between their phases. The distributedloop comprises at least one clock divider, a phase detector, and avariable delay element (phase aligner). For example, clock dividers areused to divide down the clocks that define the clock domains to a commonfrequency. The divided clocks drive a phase detector, which drives aphase aligner. The distributed loop shifts the phase of one of thedivided clocks to align it with the other divided clock. When thedivided clocks are phase aligned by the distributed loop, the originalclocks will have edges which are also phase aligned. Data can then betransferred at the aligned clock edges without incurring additionallatency for synchronization.

[0020] In one embodiment, in order to reduce power consumption in a lowpower mode, the output of a clock generator is disabled withoutdisabling the clock generator in its entirety. This eliminates the powerrequired to drive the load on the clock line, while avoiding frequencyand phase drift, thus eliminating the latency normally required tore-acquire frequency and phase lock when coming out of a low power mode.This is accomplished by separating the phase alignment feedback andfrequency lock feedback in one embodiment.

[0021] In addition, multiple clock domains are provided in oneembodiment, which are separately synchronized. This, for example, allowsclock domains not in use to be powered down. Also, simultaneoussynchronization among multiple clock domains will permit transfersbetween more than two clock domains at the same time.

[0022] Therefore, the invention allows for synchronization of differentclock domains, while minimizing the amount of latency resulting from anyadditional synchronization latency. A further understanding of thenature and advantages of the present invention may be realized byreference to the latter portion of the specification and attacheddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] For a better understanding of the invention, reference should bemade to the following detailed description taken in conjunction with theaccompanying drawings, in which:

[0024]FIG. 1 is a block diagram of a prior art single clock systemarchitecture;

[0025]FIG. 2 is a block diagram of an alternate prior art system clockarchitecture;

[0026]FIG. 3 shows the clock waveforms of an example gear ratiorelationship;

[0027]FIG. 4 is a block diagram of a memory system with two clockdomains;

[0028]FIG. 5 is a block diagram of an example gear ratio logic block;

[0029]FIG. 6 is a block diagram of an example gear ratio logicsub-block;

[0030]FIG. 7 is a block diagram of an example of a different gear ratiologic sub-block;

[0031]FIG. 8 is a block diagram of an alternate example of a gear ratiologic sub-block;

[0032]FIG. 9 is a timing diagram of gear ratio logic signals for a 3/2gear ratio;

[0033]FIG. 10 shows a simplified block diagram of a memory controllerlogic block;

[0034]FIG. 11 shows a timing diagram for transfers in the writedirection for a 3/2 gear ratio example;

[0035]FIG. 12 shows a timing diagram for transfers in the read directionfor a 3/2 gear ratio example;

[0036]FIG. 13 shows a timing diagram for transfers in the writedirection for a 4/3 gear ratio example;

[0037]FIG. 14 shows a timing diagram for transfers in the read directionfor a 4/3 gear ratio example;

[0038]FIG. 15 shows a timing diagram for transfers in the writedirection for a 5/3 gear ratio example;

[0039]FIG. 16 shows a timing diagram for transfers in the read directionfor a 5/3 gear ratio example;

[0040]FIG. 17 is a block diagram of an equivalent circuit for aDependent Clock Generator;

[0041]FIG. 18 is a block diagram of a Distributed Clock Generator Loop;and

[0042]FIG. 19 is a block diagram of an alternative Distributed ClockGenerator Loop applied to multiple clock domains.

[0043] Like reference numerals refer to corresponding parts throughoutthe drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] One aspect of the present invention applies where the clockperiods (or frequencies) of two domains of digital logic have a fixedratio. When this relationship holds, the two domains are said to beoperating in a gear ratio fashion. Therefore, two clocks can be said tohave a gear ratio when an integer multiple of the first clock's periodequals the same amount of time as an integer multiple of the secondclock's period. For example, two clocks have a 4/3 gear ratio if fourcycles of the first clock equal three cycles of the second clock.

[0045]FIG. 3 shows the clock waveforms of an example gear ratio wherethree cycles of clock PCLK_C 302 equal two cycles of clock SCLK_C 304,or 3* (cycle of PCLK_C)=2* (cycle of SCLK_C). In FIG. 3, PCLK_C 302 andSCLK_C 304 are phase aligned at the end of the common period, forexample by being generated from the same crystal. Since gear ratio isdefined as the ratio of the two clock frequencies, in the above examplethe gear ratio of PCLK_C/SCLK_C is 3/2. If clock signals PCLK_C 302 andSCLK_C 304 are divided by 6 and 4, respectively, a clock signal 306 willresult which is equal to both PCLK_C/6 or SCLK_C/4.

[0046]FIG. 4 shows a block diagram of a digital system with two clockdomains operating in gear ratio fashion. The digital system is a MemoryControl Unit 405. An external clock signal PCLKEXT 410 supplies a clocksignal PCLK 415 through buffers 412 to an Application Logic block 420inside Memory Control Unit 405.

[0047] A set of signals 425 are developed within the domain of PCLK 415.The “/” symbol on each of the lines indicates that the signal may be asingle line or a bus. On each edge of PCLK 415, signals and buses 425communicate all the information needed to initiate a memory transaction(read or write operation) in memory devices 430. Signal A 435 contains atransaction address. Signal C 440 contains control codes to selectoptions and operations. Signal W 445 contains transaction write data.And, signal R 450 contains transaction read data.

[0048] A memory controller 455 also operates in the domain of PCLK 415.It uses a set of buses 460 to communicate with a Memory Interface Logic465. A signal TROW 467 contains transaction controls and addresses forrow operations. A signal TCOL 469 contains transaction controls andaddresses for column operations. A signal TD 471 contains transactionwrite data. A signal RD 473 contains transaction read data. Buses 460carry the same information as was on buses 425, but in a format that canbe directly utilized by memory devices 430.

[0049] Memory Interface Logic 465 operates in the domain of SCLK 475.Subsystems of memory devices 430 also (effectively) operate in thedomain of SCLK 475. SCLK 475 and PCLK 415 are in a gear ratiorelationship. They both drive gear ratio Logic 477, generating signalsSPHASE 471 and PPHASE 481, which measure the relative phase of PCLK 415and SCLK 475. These two phase signals are driven to a Dependent ClockGenerator 483. The phase difference is measured and used to drive clocksignal CTM 485.

[0050] CTM 485 drives a signal CFM 487 for memory devices 430 andultimately becomes SCLK 475 for Memory Interface Logic 465. The feedbackloop from gear ratio Logic 477 through clock generator 483 and MemoryInterface Logic 465 allows the phase (and frequency) of SCLK 475 toautomatically adjust to a known relationship with PCLK 415. Clockgenerator 483 could be a component external to Memory Control Unit 405or, alternatively, a block within it. The first case is shown in FIG. 4.

[0051] Signals TROW 467, TCOL 469, TD 471, and RD 473 are converted intoDQ 489 and RQ 491 which form bus 493 between Memory Interface Logic 465and memory devices 430. The details of this format conversion do notaffect this disclosure, and will not be discussed further.

[0052]FIG. 5 shows an example of details within a gear ratio Logic block477 of FIG. 4. Elements appearing in FIG. 5 which were introduced inFIG. 4 are referred to with the same reference numerals which wereoriginally used.

[0053] In FIG. 5, there are two similar sub-blocks 510 and 520, one forPCLK 415 and one for SCLK 475, respectively. PCLK sub-block 510 dividesPCLK 415 by M. Similarly, sub-block 520 divides SCLK 475 by N. The valueof M and N specify a desired gear ratio. These values could be, forexample, set by initialization registers through PCTL 530 and SCTL 540,respectively. In general, M is double the value of PCTL+1 and N isdouble the value of SCTL+1. For example, as shown in FIG. 3, a 3/2 gearratio will require M=6, N=41 PCTL=2, and SCTL=1. PCTL 530 may be up to Lwide and SCTL 540 may be up to P wide.

[0054]FIG. 6 shows an equivalent circuit for sub-block 510 of FIG. 5. InFIG. 6, counter 610 is incremented on each edge of PCLK 415. Counter 610is cleared by a signal PEQ 620 whenever a comparator block 630 reaches amaximum value set by PCTL 530. Therefore, the output of counter 610,PCOLOR 550, is incremented on each edge of PCLK 415 until it reaches amaximum value set by PCTL 530.

[0055] Also, whenever PEQ 620 is asserted, the value of PPHASE 481 istoggled by a storage block 640. As a result, PPHASE 481 is assertedwhile counter 610 is counting and toggled each time counter 610 isreset. This process ensures that PPHASE 481 is indicative of theprogress of the color coding scheme. As discussed before, color codingensures data is transferred at correct edges.

[0056]FIG. 7 shows an equivalent circuit for sub-block 520 of FIG. 5.The operation of this circuit is identical to the one of FIG. 6.However, in FIG. 7, a counter 710 is incremented on each edge of SCLK475 and cleared by comparator 720 whenever a maximum value set by SCTL540 is reached. Therefore, the output of counter 710, SCOLOR 560, isincremented on each edge of SCLK 475 until it reaches a maximum valueset by SCTL 540. Also, whenever SEQ 730 is asserted, the value of SPHASE479 is toggled by a storage block 740. As a result, in FIG. 7, SPHASE479 is asserted while counter 710 is counting and toggled when counter710 is reset. This process ensures that SPHASE 479 is indicative of theprogress of the color coding scheme.

[0057]FIG. 8 shows yet another equivalent circuit for sub-block 510 ofFIG. 5. In FIG. 8, counter 610 of FIG. 6 has been replaced with an adder810 and a storage block 815. PCOLOR 550 is incremented by adder 810through storage block 815 on each edge of PCLK 415. PCOLOR 550 iscleared by a signal PEQ 820 whenever a comparator block 830 reaches amaximum value set by PCTL 530. Whenever PEQ 620 is asserted, the valueof PPHASE 481 is toggled by a storage block 840. This process ensuresthat PPHASE 481 is indicative of status of the color coding scheme inprogress.

[0058]FIG. 9 shows a timing diagram of signals associated with gearratio Logic 477 with a 3/2 gear ratio. In FIG. 9, the cycle time of SCLK475 is 3/2 times the cycle time of PCLK 415. PCOLOR 550 is incrementedfrom a value 000 through a value 010 (i.e., 000, 001, 010) on each edgeof PCLK 415. When PCOLOR 550 reaches a maximum value 010, PCOLOR 550clears to 000 and PEQ 620 is asserted. PEQ 620, in turn, toggles thevalue of PPHASE 481. Therefore, PPHASE signal 481 alternates from 0 to 1every three cycles of PCLK 415, or one cycle Tccyc 910.

[0059] On the other hand, SCOLOR 560 reaches a maximum value of 001, forthis example. Once SCOLOR 560 reaches 001, the value of SCOLOR 560clears to 000 and SEQ 730 is asserted. SEQ 730, in turn, toggles thevalue of SPHASE 479. Thus, SPHASE 479 alternates from 0 to 1 every twocycles of SCLK 475, or one cycle TCCYC 910.

[0060] In a 3/2 embodiment, PCOLOR 550 and SCOLOR 560 indicate the valueof counts in progress for PCLK 415 and SCLK 475, respectively. PCOLOR550 is asserted for three cycles of PCLK 415 (as shown by encircled 1,2, and 3) and SCOLOR 560 is asserted for two cycles of SCLK 475 (asshown by encircled 1 and 2).

[0061] The values of PCOLOR 550 and SCOLOR 560 are used in at least twoways. First, the values of PCOLOR 550 and SCOLOR 560 are used to assertPPHASE 481 and SPHASE 479, respectively, to phase-align, for example,SCLK 475 to PCLK 415 at the proper edges for a given gear ratioconfiguration. PPHASE 481 and SPHASE 479 are asserted whenever theircoloring signals indicate a counting in progress. For example, PPHASE481 is toggled each time PCOLOR 550 is reset; and, SPHASE 479 is toggledeach time SCOLOR 560 is reset. Therefore, PPHASE 481 and SPHASE 479measure the relative phase of PCLK 415 and SCLK 475. Furthermore, asshown in FIG. 4, PPHASE 481 and SPHASE 479 are driven to a clockgenerator 483 which drives clock signal CTM 485. Hence, clock CTM 485will become a phase-aligned clock signal derived from SCLK 475.

[0062] Second, the value for PCOLOR 550 is used to indicate when dataread and write operations should take place. Further details on the useof PCOLOR 550 are described below with respect to FIG. 10.

[0063] Other gear ratios are possible. For example, with two 3-bit colorregisters, about 64 gear ratio combinations are possible because eachregister will have eight possible different combinations. However, someof these combinations will be redundant.

[0064] Thus, as shown in FIG. 9, if PCLK 415 cycle time is shorter thanSCLK 475 cycle time, and if PCLK and SCLK have a known frequency andphase relationship, then there is a systematic process that can befollowed, which allows a single memory controller 455 to support a widerange of gear ratios and operate in the domain of PCLK 415.

[0065]FIG. 10 shows a simplified block diagram of memory controller 455of FIG. 4. There are five buffer and logic blocks which have beendesigned to operate at PCLK 415 frequency. As shown, W 445, A 435, C440, and START 1010 inputs are accepted by blocks 1020 and 1030. Theseinputs are used with current values stored in these blocks to produce TD471, TROW 467, TCOL 469, RRDY 1040, GETC 1050, and WRDY 1060. START 1010is a handshake signal indicating a valid value of A 435 and C 440. RRDY1040 is a strobe signal indicating a valid value of R 450. GETC 1050 isa handshake signal indicating that the contents of A 435, C 440, and W445 are accepted. And, WRDY 1060 is a strobe signal indicating a validvalue of W 445. These signals are used together to perform a read orwrite operation in memory controller 455.

[0066] A PCLKEN Logic 1065 uses PCOLOR 550 to develop two signals,PCLKENT 1070 and PCLKENR 1080. PCLKENT 1070 is applied to blocks 1020,1030, and 1090 to indicate that a write transfer is enabled. Forexample, when PCLKENT 1070 is a one, the value of blocks 1020 and 1030are updated with new input values. Conversely, when PCLKENT 1070 iszero, the current value of buffers 1020 and 1030 are recirculated.

[0067] Moreover, enable signal PCLKENR 1080 is also developed by PCLKENLogic 1065. PCLKENR 1080 is also applied to blocks 1095 and 1090 toindicate that a read transfer is enabled. When PCLKENR 1080 is a one,the value of buffer 1095 is updated. Conversely, a zero value of PCLKENR1080 results in recirculating the current values stored in buffer 1095.

[0068]FIG. 11 shows a timing diagram for transfers from the domain ofPCLK 415 to the domain of SCLK 475, using a 3/2 gear ratio. In FIG. 11,signal PCLKENT 1070 is asserted when the value of PCOLOR 550 is 001 or010; and, is toggled off when the value is 000. As a result, the valueof PCLKENT 1070 indicates when data may be transferred from the domainof PCLK 415 to the domain of SCLK 475.

[0069] A signal TREG 1110 is a simplified representation for the valuesof signals TD 471, TROW 467, and TCOL 469. As shown, due to the state ofPCLKENT 1070, TREG 1110 will keep its value (i.e. T1, T2, T3, and T4)for either one or two cycles of PCLK 415. The setup time for transfer ofthe data contained in TREG 1110 is shown by a corresponding tSu in FIG.11. For example, tSu 1130 is the setup time for transferring T1 from thedomain of PCLK 415 to the domain of SCLK 475.

[0070] Data, then, is read into Memory Interface Logic 465, representedby a signal SREG 1120, from a rising edge of PCLK 415 to the next risingedge of SCLK 475. This means that when the signals of TREG 1110 aresampled by Memory Interface Logic 465 on a rising edge of SCLK 475,there will be either one cycle of PCLK 415 or SCLK 475 for the data tobe driven from the domain of PCLK 415 and to be received by the domainof SCLK 475.

[0071] Consequently, as long as the cycles of PCLK 415 or SCLK 475,gated by PCLKENT 1070, are used, the result will be the same whencounting intervals for tracking the progress of a transaction throughmemory devices 430. In accordance with the color coding scheme utilized,PCLKENT 1070, being derived from PCOLOR 550, will indicate at what clockedges data may be reliably transferred from the domain of PCLK 415 tothe domain of SCLK 475. This is important because it means that thelogic needs to be designed and optimized just once. All that may need tobe changed is the color coding scheme to achieve a more optimized resultfor a given gear ratio.

[0072] Thus, the logic can be used with any gear ratio combination aslong as the cycle time of PCLK 415 is shorter than the cycle time ofSCLK 475. This last restriction is needed because it is assumed thatmemory controller 455 needs to produce information on every edge of SCLK475 for Memory Interface Logic 465 to keep memory devices 430 active atall times. This is the case because, as a practical matter, most memorydevices 430 are slower than components in the domain of PCLK 415. Sincememory devices such as 430 take more time to finish a given operation,they may need to be active for longer periods to keep up with the restof the circuitry.

[0073] In a similar fashion to PCLKENT 1070, signal PCLKENR 1080 isneeded for communication from the domain of SCLK 475 to the domain ofPCLK 415. The only information flowing in this direction is the readdata.

[0074]FIG. 12 shows a timing diagram for transfers from the domain ofSCLK 475 to the domain of PCLK 415, using a 3/2 gear ratio. PCLKENR 1080is asserted whenever the value of PCOLOR 550 is 000 or 010, and toggledoff when the value of PCOLOR 550 is 001. Read data is driven by memorydevices 430 through Memory Interface Logic 465. In this embodiment,signal PCLKENR 1080 uses the value of PCOLOR 550 to ensure that as muchtime as possible is available for crossings from the domain of SCLK 475to the domain of PCLK 415.

[0075] As shown in FIG. 12, there will be either one cycle of PCLK 415(i.e., for S1) or one cycle of SCLK 475 (i.e., for S2) available todrive the read data from the domain of SCLK 475. The setup time fortransfer of each value of SREG 1120 is shown by a corresponding tSU inFIG. 12. For example, tSU 1210 is the setup time for transferring the S1data. Data is then read into memory controller 455 on selected edges ofPCLK 415. For example, S1 is read from a rising edge of SCLK 475 to thenext rising edge of PCLK 415 and S2 is read from a rising edge of SCLKto the second following rising edge of PCLK 415.

[0076]FIG. 13 shows a timing diagram for transfers from the domain ofPCLK 415 to the domain of SCLK 475, using a 4/3 gear ratio. In FIG. 13,PCOLOR 550 cycles through four values (i.e., 000, 001, 010, and 011).For PCLKENT 1070, the value 000 of PCOLOR 550 is not used (as with the3/2 example). The value of PCLKENT 1070 indicates when data may betransferred from the domain of PCLK 415 to the domain of SCLK 475. Thevalues used are different in the 4/3 case because each coloring value isselectively used based on combinations which provide the best timing fortransfers. As a result, the coloring codes might differ from one case tothe next. However, as discussed before, the logic only needs to bedesigned once.

[0077] The setup time for transferring the data contained in TREG 1110is shown by a corresponding tSu in FIG. 13. For example, tSU 1310 is thesetup time for transferring T4 from the domain of PCLK 415 to the domainof SCLK 475. As shown, in the 4/3 example, the time available for datatransport from the domain of PCLK 415 to SCLK 475 is one cycle of SCLK475, ½ cycle of SCLK 475, and one cycle of PCLK 415 (for T4, T5, and T6,respectively). The second transport slot (T5) has the least amount ofsetup time.

[0078]FIG. 14 shows a timing diagram for transfers from the domain ofSCLK 475 to the domain of PCLK 415, using a 4/3 gear ratio. In FIG. 14,PCOLOR 550 cycles through four values (i.e., 000, 001, 010, and 011).For PCLKENR 1080, the value 010 of PCOLOR 550 is not used (which differsfrom the 3/2 example). The value of PCLKENR 1080 indicates when data maybe transferred from the domain of SCLK 475 to the domain of PCLK 415.The values used are different in the 4/3 case because each coloringvalue is selectively used based on combinations which provide the besttiming for transfers. As a result, the coloring codes might differ fromone case to the next. However, as discussed before, the logic only needsto be designed once.

[0079] The setup time for transfer of the data contained in SREG 1120 isshown by a corresponding tSu in FIG. 14. For example, tsU 1410 is thesetup time for transferring S3 from the domain of SCLK 475 to the domainof PCLK 415. As shown, in the 4/3 example, the time available for datatransport from the domain of SCLK 475 to PCLK 415 is one cycle of PCLK415, ½ cycle of SCLK 475, and one cycle of SCLK 475 (for S3, S4, and S5,respectively). Again, the second transport slot (S4) has the leastamount of setup time.

[0080]FIG. 15 shows a timing diagram for transfers from the domain ofPCLK 415 to the domain of SCLK 475, using a 5/3 gear ratio. In FIG. 15,PCOLOR 550 cycles through five values (i.e., 000, 001, 010, 011, and100). For PCLKENT 1070, the values 000 and 010 of PCOLOR 550 are notused. Again, the value of PCLKENT 1070 indicates when data may betransferred from the domain of PCLK 415 to the domain of SCLK 475. Thevalues used are different in the 5/3 case because each coloring value isselectively used based on combinations which provide the best timing fortransfers. As a result, the coloring codes might differ from one case tothe next. However, as discussed before, the logic only needs to bedesigned once.

[0081] The setup time for transfer of the data contained in TREG 1110 isshown by a corresponding tSu in FIG. 15. For example, tSu 1510 is thesetup time for transferring T4 from the domain of PCLK 415 to the domainof SCLK 475. As shown, in the 5/3 example, the time available for datatransport from the domain of PCLK 415 to SCLK 475 is one cycle of SCLK475, one cycle of SCLK 475, ⅘ cycle of SCLK 475, and one cycle of PCLK415 (for T4, T5, and T6, respectively). The third transport slot (T6)has the least amount of setup time in this example.

[0082]FIG. 16 shows a timing diagram for transfers from the domain ofSCLK 475 to the domain of PCLK 415, using a 5/3 gear ratio. In FIG. 16,PCOLOR 550 cycles through five values (i.e., 000, 001, 010, 011, and100). For PCLKENR 1080, the values 001 and 011 of PCOLOR 550 are notused. The value of PCLKENR 1080 indicates when data may be transferredfrom the domain of SCLK 475 to the domain of PCLK 415. The values usedare different in the 5/3 case because each coloring value is selectivelyused based on combinations which provide the best timing for transfers.As a result, the coloring codes might differ from one case to the next.However, as discussed before, the logic only needs to be designed once.

[0083] The setup time for transfer of the data contained in SREG 1120 isshown by a corresponding tSU in FIG. 16. For example, tSU 1610 is thesetup time for transferring S3 from the domain of SCLK 475 to the domainof PCLK 415. As shown, in the 5/3 example, the time available for datatransport from the domain of SCLK 475 to PCLK 415 is one cycle of PCLK415, 4/5 cycle of SCLK 475, and one cycle of SCLK 475 (for S3, S4, andS5, respectively). The first transport slot (S3) has the least amount ofsetup time.

[0084] As shown in FIGS. 13 through 16, the timing margins are betterfor a 5/3 gear ratio than for a 4/3 gear ratio, even though PCLK 415 isrunning relatively faster than SCLK 475.

[0085] In general, even if two clocks are related by a gear ratio, thereis no inherent phase relationship between the clocks. This being thecase, their clock edges may never be aligned. As previously discussed,if some method exists to align one rising edge of SCLK 415 to one of therising edges of PCLK 475, then a synchronized phase relationship, suchas shown in FIG. 3, can be achieved.

[0086] Therefore, there are known time periods when data transactionsare allowed in a gear ratio system, as well as known periods of timewhen transactions are not allowed. As a practical matter, since memorycomponents (in the domain of SCLK 475) are generally slower than theother components in the domain of PCLK 415, during the periods when datatransactions are allowed, larger than required blocks of data can betransferred in order to keep the logic in the domain of SCLK 475 activeduring the cycles when data transfer is not allowed. Therefore, foroptimization purposes, the components in the domain of SCLK 475 may needto be kept active even when no data is arriving from the domain of PCLK415.

[0087]FIG. 17 shows an equivalent circuit for Dependent Clock Generator483 of FIG. 4. Gear ratio Logic 477 of FIG. 4 develops PPHASE 481 andSPHASE 479 which are compared by phase comparator 1710. Phase comparator1710, in turn, drives a voltage controlled oscillator (VCO) 1720. VCO1720 provides CTM 485 which effectively becomes SCLK 475, as shown inFIG. 4.

[0088]FIG. 18 shows a distributed clock generator Loop 1810 which is analternative equivalent circuit for Dependent Clock Generator 483 of FIG.4. The architecture contains a clock source 1820, a distributed clockgenerator (DCG) 1825, and Memory Control Unit 405 with logic running intwo clock domains, PCLK 415 and SCLK 475.

[0089] In one embodiment, clock source 1820 in FIG. 18 generates all ofthe clock frequencies required by the system, including PCLKEXT 410 forMemory Control Unit 405 and a reference clock for the distributed loop,REFCLK 1830. However, this is only one embodiment and REFCLK 1830 couldbe generated by a different clock source than PCLKEXT 410.

[0090] In the general case, PCLKEXT 410 and REFCLK 1830 could bedifferent frequencies or the same frequency, or even could be combinedinto one signal. Also, REFCLK 1830 could be completely derived from adifferent clock source than PCLKEXT 410. PCLKEXT 410 is buffered insideMemory Control Unit 405 by buffers 1835 to generate PCLK 415.Alternately, PCLKEXT 410 could be divided down or multiplied up togenerate PCLK 415. But, the control logic that runs Memory Control Unit405 is generally all in the domain of PCLK 415.

[0091] DCG 1825 receives REFCLK 1830. REFCLK 1830 is multiplied byutilizing clock dividers, 1893 and 1895, and a phase-locked loop (PLL)1840 to generate a higher frequency clock. No specific type of PLLdesign is required for the distributed clock loop. One of skill in theart would understand that any one of a number of PLL designs of theprior art may be employed. The output of PLL 1840 is passed to a phasealigner 1845. No specific type of phase aligner design is required forthe distributed clock loop. One of skill in the art would understandthat any one of a number of phase aligner designs of the prior art maybe employed.

[0092] As a result, the output frequency of phase aligner 1845 is thesame as its input frequency, but the output phase is delayed from theinput phase by an amount determined by a control input 1850. The outputof phase aligner 1845 is buffered by an output driver 1855 and drivenout of DCG 1825 as signal CTM 485. In general, CTM could be any type ofclock signal including a small-swing differential clock or asingle-ended CMOS-level clock.

[0093] In FIG. 18, CTM 485 is shown traveling down a transmission linepast Memory Control Unit 405 to a termination resistor 1860. The use ofterminated transmission lines is common practice in high-speed clockdistribution, but is not a requirement for the distributed clock loop.In FIG. 18, CTM 485 is passed to a delay locked loop (DLL) block 1865inside the I/O section of Memory Control Unit 405. DLL 1865 is used toremove skew from clock signals distributed within the I/O circuitry. Theuse of DLLs inside controllers is preferable but not a requirement forthe distributed clock loop architecture.

[0094] Finally, the output of DLL 1865 drives a clock divider, C 1870,which divides CTM 485 to generate SCLK 475. A common value for thedivider C would be four, but C could be any value including one (i.e.,SCLK=CTM). In FIG. 18, all of the logic on the inside portion of the I/Osection of Memory Control Unit 405 runs in the same domain of SCLK 475.

[0095] Also in FIG. 18, there are two clock dividers in the gear ratioLogic, M 1875 and N 1880. Clock divider 1875 divides PCLK 415 togenerate PCLK_M 1885, and clock divider 1880 divides SCLK 475 togenerate SCLK_N 1890. The two divided clocks, PCLK_M 1885 and SCLK_N1890, are output from Memory Control Unit 405 and passed back to DCG1825 as inputs to a phase detector 1892. In one embodiment, PCLK_M 1885and SCLK_N 1890 may need to be carefully matched since they are routedbetween chips and may introduce timing skew between PCLK 415 and SCLK475.

[0096] Phase detector 1892 compares the relative phases of PCLK_M 1885and SCLK_N 1890, and outputs an error signal on 1850. PCLK_M 1885 andSCLK_N 1890 may be substituted for PPHASE 481 and SPHASE 479 of FIG. 4,respectively. Output 1850 could be either a proportional error signal(indicating the amount of error) or a simple early/late signal (i.e., abang-bang loop). Phase detector output 1850 drives phase aligner 1845 toeither increase or decrease its delay. When the output phase of phasealigner 1845 changes, the phase of CTM 485 will have the same amount ofphase change. The phase of SCLK 475 also will have the same phasechange, and eventually the phase of SCLK_N 1890 will follow. Thus, phasedetector 1892 drives phase aligner 1845 to adjust the phase of SCLK_N1890 until it matches the phase of PCLK_M 1885, and the phase error isminimized.

[0097]FIG. 18 shows one embodiment of the distributed clock generationloop. Other arrangements of the blocks of the distributed loop arepossible. For example, phase detector 1892 could be placed in MemoryControl Unit 405 instead of in DCG 1825. Optionally, PLL 1840 may beomitted from DCG 1825 if not required. As mentioned previously, DLL 1865and divider C 1870 may be omitted from the I/O portion of Memory ControlUnit 405 if not required, or placed outside of Memory Control Unit 405.The other clock buffers such as 1835 are also optional. The M and Ndividers, 1875 and 1880, respectively, could have any divisor includingone. A 1/1 gear ratio could be formed by using M=N=2 if the frequenciesof PCLK 415 and SCLK 475 were equal. As discussed before with respect toFIG. 5, the values of M and N are double the values of PCTL+1 andSCTL+1, respectively. However, an effective 1/1 gear ratio could also beformed by using M=N=4. This would still keep PCLK_M 1885 equal to SCLK_N1890 but would lower the frequency of the divided-down clock signals.The lower frequency might be helpful for the best phase detectionperformance by phase detector 1892. Also, because of the feedback loop,a higher frequency of PCLK_M 1885 and SCLK_N 1890 will generate aquicker response from the feedback loop and may result in more jitter inthe circuit, for example.

[0098] In FIG. 18, there are also two additional clock dividers, A 1893and B 1895, coupled to the inputs of PLL 1840. Clock divider 1895divides REFCLK 1830 by B, and clock divider 1893 divides the output ofPLL 1840 by A before it is fed back to the input of PLL 1840. Theseclock dividers will force PLL 1840 to multiply the frequency of REFCLK1830 by the ratio A/B, so that the PLL output clock will equalREFCLK*A/B. The frequency of CTM 485 is the same as the output frequencyof PLL 1840 because phase aligner 1845 does not affect the clockfrequency (only phase).

[0099] Also, the input of phase detector 1892, SCLK_N 1890, is dividedfrom CTM 485 by dividers 1870 and 1880. Therefore, SCLK_N 1880 isrelated to REFCLK 1830 by the following relationship:

SCLKN_N=REFCLK*A/(B*C*N)

[0100] For example, if REFCLK 1830 is 50 MHz, and if dividers 1870,1880, 1893 and 1895 are set such that A=8, B=1, C=4, and N=4, thenSCLK_N 1890 will be 25 MHz. Some other examples of frequencies for PCLK415 and REFCLK 1830, with various combinations of dividers for A 1893, B1895, M 1875, and N 1880, and the resulting frequencies for CTM 485 andSCLK 475 are shown in Table 1. The values in Table 1 have been roundedoff. The value of C is kept at 4 for all cases shown. The column labeled“F@PD” gives the frequency into phase detector 1892, which is thefrequency for both PCLK_M 1885 and SCLK_N 1890. TABLE 1 REF- PCLK CLKCTM SCLK Gear F@PD (MHz) (MHz) (MHz) (MHz) A B M N Ratio (MHz) 67 33 26767 8 1 2 2 1/1 33 100 50 300 75 6 1 8 6 4/3 12.5 100 50 400 100 8 1 4 42/2 25 125 50 300 75 6 1 10 6 5/3 12.5 133 67 267 67 4 1 4 2 2/1 33 133133 356 89 8 3 6 4 3/2 22 133 67 400 100 6 1 8 6 4/3 16.7 150 150 400100 8 3 6 4 3/2 25 200 100 400 100 4 1 8 4 4/2 25

[0101] In one example, a single oscillator, MAIN CLK SRC 1820, isdivided one way to create a high frequency clock, PCLK 415, for MemoryControl Unit 405, and is divided another way to create a referenceclock, REFCLK 1830, for the memory subsystem. If a fast memory systemclock of, say, 400 MHz is desired for the memory bus transfers, a slowerclock for generating an accurate phase detector output 1850 and dataenable signals may be needed, so the 400 MHz is divided by C=4 togenerate a 100 MHz SCLK clock.

[0102] The M and N dividers, 1875 and 1880, select a frequency intowhich both PCLK 415 and SCLK 475 are divisible. In the example of FIGS.9 and 11, M=6 and N=4 results in two signals PPHASE 481 and SPHASE 479with the common frequency. These can then be aligned in phase aligner1845.

[0103] It is desirable to be able to turn off the clock drive lines andtheir capacitive loads to reduce power consumption. But this wouldnormally lose frequency and phase lock on the clock, requiring a longlatency for reacquiring lock when coming out of a low power state. Theinvention provides a way to maintain frequency lock, and only requirephase lock when coming out of a low power state. This is done bycreating a separate frequency lock with PLL 1840. Thus, when thefeedback loop to phase aligner 1845 is turned off in low power,frequency lock at the desired common frequency corresponding to the Mand N values, with the C divider factored in, is maintained with PLL1840 and dividers 1875 and 1880.

[0104] Also shown in FIG. 18 are two output multiplexers 1894 and 1896.Output multiplexer 1894 selects between the output of PLL 1840 and theoutput of phase aligner 1845 under control of a select signal SELECT1897. Selecting the output of phase aligner 1845 is the normal mode ofoperation of the distributed loop. However, selecting the output of PLL1840 bypasses phase aligner 1845 and disables the distributed loop. Thismode would be useful, for example, for testing the output of PLL 1840directly.

[0105] Output multiplexer 1896 in FIG. 18 enables output driver 1855under the control of an output enable signal OUTEN 1898. The output ofdriver 1855 is enabled by output multiplexer 1896 in the normal mode ofoperation of the distributed loop. The OUTEN 1898 signal can disable theoutput either by switching the output to drive a low logic level (asshown) or by switching the output into a high-impedance state. When theoutput is disabled, no power is dissipated in the output driver stage,and significant power is saved. This feature of the present inventionwill be, for example, very helpful in portable applications where thereduction of power consumption is highly desirable. This also enablesthe distributed loop to avoid frequency and phase drifts for alow-latency startup, while eliminating the power drain of driving thecapacitive load on the clock line of CTM 485.

[0106] Moreover, traditional PLLs have long acquisition and settlingtimes. If the feedback loop is broken in a traditional PLL (for example,by disabling the clock signal), the output clock frequency would driftsignificantly from the locked condition and significant time would berequired to re-lock the loop. For example, a traditional PLL mightrequire 10 microseconds to re-lock the loop if the feedback clock weredisabled. However, for the distributed clock generation loop shown inFIG. 18, the feedback clock to divider 1893 is not broken when theoutput clock is disabled at multiplexer 1896 because the output of PLL1840 is still fed back to divider 1893. Therefore, there is no clockfrequency drift when the output clock is disabled and the delay istherefore less when the output is enabled again.

[0107] Furthermore, phase aligners have a much shorter acquisition andsettling times than traditional PLLs. Since the phase aligner block onlyadjusts the phase and does not affect the clock frequency, there is noclock frequency or phase drifts when the output clock is disabled.Therefore, when the output clock is re-enabled by multiplexer 1896,signals 1890 and 1885 at the inputs to phase detectors 1892 will returnto their previously locked state relatively quickly. For example, theoutput clock from the distributed DLL loop might settle in less than 10nanoseconds (or a few clock cycles), as compared to 10 microseconds forthe traditional PLL.

[0108]FIG. 19 shows how the distributed clock architecture could beapplied to a system in order to interface a single clock domain withmultiple clock domains. Elements appearing in FIG. 19 which wereintroduced in previous figures are referred to with the same referencenumerals which were originally used.

[0109] In one embodiment, clock source 1905, in FIG. 19, generates allof the clock frequencies required by the system, including PCLKEXT 410for Memory Control Unit 1915 and a reference clock for the distributedloop, REFCLK 1910. However, this is only one embodiment and REFCLK 1910could be generated by a different clock source than PCLKEXT 410.

[0110] PCLKEXT 410 is buffered by buffers 1920 to produce PCLK 415,which is divided by M when it passes through divider 1925 to producePCLK_M 1930. But, in FIG. 19, REFCLK 1910 is routed to two DCG blocks1935 and 1940, each of which produce corresponding output clocks, CTM11942 and CTM2 1944, which in turn generate corresponding I/O outputclocks, SCLK1 1946 and SCLK2 1948. These clocks are fed to theircorresponding dividers, N1 1950 and N2 1952, to produce two clocks,SCLKl_N1 1954 and SCLK2_N2 1956, for two loop phase detectors 1958 and1960, respectively.

[0111] In principle, the two N dividers could have different values, andthe two distributed loops could run at different frequencies. Forexample, it would be possible to have PCLK=100 MHz, SCLK1=75 MHz, andSCLK2=100 MHz. However, in most practical applications, the frequenciesof SCLK1 1946 and SCLK2 1948 would be identical, and the dividers N11950 and N2 1952 would have the same value (i.e., N1=N2).

[0112] In FIG. 19, phase detectors 1958 and 1960 drive their respectivephase aligners 1962 and 1964 to shift the phase of their correspondingSCLKs until both SCLK1_N1 1945 and SCLK2_N2 1956 are aligned with PCLK_M1930. When these two loops are independently aligned, the control logicin the domain of PCLK 415 can talk to both of the I/O clock domains 1970and 1972 simultaneously using the gear ratio technique discussedpreviously. In this manner, distributed clock loops can be used togenerate the clocks required to allow asynchronous data transfers acrossmultiple clock domains (i.e., two or more) with minimized latency. Also,multiple clock domains allows some to be turned-off to save power ifonly part of the memory is being used.

[0113] In conclusion, methods and circuitry are disclosed for applyinggear ratio techniques to allow data exchange between different clockdomains with minimal latency. Also, methods and circuitry are disclosedfor a distributed clock generation loop which generates clocks requiredto allow asynchronous data transfers with minimized latency.

[0114] While the above is a complete description of the preferredembodiments of the invention, various alternatives, modifications, andequivalents may be utilized. For example, the disclosed techniques couldbe used to simultaneously synchronize multiple clock domains to aprincipal clock domain. Also, the use of the distributed clockgeneration loop of the present invention is not limited to memorysubsystems, and could be applied to other applications which requiredata transmission between multiple clock domains. Therefore, the abovedescription should not be taken as limiting the scope of the inventionwhich is defined by the appended claims.

What is claimed is:
 1. A method, executed in a memory control unit, oftransferring data between two clock domains having first and secondclock signals related by a gear ratio relationship in a common period,said method comprising the steps of: marking a particular period offirst and second clock signals in a common period to produce a markedperiod for data transfer between two clock domains such that a datatransfer occurs for every cycle of a slower one of said first and secondclock signals; and transferring data between said two clock domains ofsaid memory control unit at a clock edge of said marked period.
 2. Themethod of claim 1, wherein said marking step marks a period whichminimizes latency and provides a sufficient setup period for datatransfers.
 3. The method of claim 1, wherein said marking step comprisesthe steps of: selecting a first edge of a faster one of said first andsecond clock signals in said common period for strobing data into abuffer; and selecting a next edge of a slower one of said first andsecond clock signals in said common period for strobing data out of saidbuffer.
 4. The method of claim 1, wherein said marking step comprisesthe steps of: selecting a first edge of a slower one of said first andsecond clock signals in said common period for strobing data into abuffer; and selecting a latest next edge of a faster one of said firstand second clock signals before a next edge of the slower clock signalin said common period for strobing data out of said buffer.
 5. Themethod of claim 1 further comprising the steps of: programming a firststorage device with a value for said gear ratio relationship, whereinsaid marking step utilizes the content of said first storage device toindicate how many periods of said first and second clock signals are insaid common period; and programming a second storage device with saidmarked period, wherein said data transfer step utilizes the content ofsaid second storage device to indicate which clock edge may be used fortransferring data between said first and second clock domains.
 6. Themethod of claim 1, wherein said gear ratio relationship is selected fromthe group consisting of 1/1, 312, 4/3, and 5/3.
 7. A method, executed ina memory control unit, of transferring data between two clock domainshaving first and second clock signals related by a gear ratiorelationship in a common period, said method comprising the steps of:marking a particular period for transfers from a slower one of two clockdomains such that a data transfer occurs for every cycle of a slower oneof first and second clock signals, including the steps of: selecting afirst edge of a slower one of said first and second clock signals in acommon period for strobing data into a buffer, and selecting a latestnext edge of a faster one of said first and second clock signals beforea next edge of said slower clock signal in said common period forstrobing data out of said buffer; marking a particular period fortransfers from a faster one of said clock domains such that a datatransfer occurs for every cycle of a slower one of said first and secondclock signals, including the steps of: selecting a first edge of afaster one of said first and second clock signals in said common periodfor strobing data into said buffer, and selecting a next edge of aslower one of said first and second clock signals in said common periodfor strobing data out of said buffer; and transferring data between saidtwo clock domains of said memory control unit at a clock edge of saidmarked period.
 8. A clock generator for generating a dependent outputclock from a reference clock, said clock generator comprising: afrequency synthesis loop circuit configured to receive a referenceclock, said reference clock having a fixed frequency, said frequencysynthesis loop configured to generate a synthesized output clock havinga frequency related to said fixed frequency of said reference clock; andphase alignment circuitry configured to receive said synthesized outputclock, a reference-phase clock, and a dependent-phase clock, saidreference-phase clock having the same frequency as the frequency of adependent-phase clock, said phase alignment circuitry configured todetect the phase difference between said reference-phase clock and saiddependent-phase clock, said phase alignment circuitry further configuredto phase-shift said synthesized output clock according to a detectedphase difference to generate a dependent output clock, wherein saiddependent output clock has the same frequency as said synthesized outputclock and is phase-shifted as a function of said detected phasedifference between said reference-phase clock and said dependent-phaseclock.
 9. The clock generator of claim 8 further comprising a clocksynchronizing circuit including gear ratio logic circuitry configured toreceive said reference and dependent output clocks and configured togenerate said reference-phase clock from said reference clock, thefrequency of said reference-phase clock being a first fraction, J/M, ofthe frequency of said reference clock, said gear ratio logic circuitryconfigured to generate said dependent-phase clock from said dependentoutput clock, the frequency of said dependent-phase clock being a secondfraction, K/N, of the frequency of said dependent output clock, whereinsaid phase alignment circuitry is configured to phase-shift saiddependent output clock such that the detected phase difference betweensaid reference-phase and dependent-phase clocks is substantially zero,wherein J, K, M, and N are selected integers.
 10. The clock generator ofclaim 9 wherein J, K, M, and N are selected from the group consisting of1, 2, 4, 6, 8, and
 10. 11. The clock generator of claim 8 wherein saidphase alignment circuitry is configured to phase-shift said dependentoutput clock such that said detected phase difference between saidreference-phase and dependent-phase clocks is substantially zero, saidclock generator further including: a main clock source configured togenerate said reference clock; gear ratio logic circuitry configured toreceive said reference clock and said dependent output clock and togenerate said reference-phase clock from said reference clock, thefrequency of said reference-phase clock being a first fraction, J/M, ofthe frequency of said reference clock, said gear ratio logic configuredto generate said dependent-phase clock from said dependent output clock,the frequency of said dependent-phase clock being a second fraction,K/N, of the frequency of said dependent output clock, wherein said gearratio circuitry is configured to generate a transfer enable signal basedon said reference and dependent output clocks, and J, K, M and N areintegers; first circuitry configured to operate in said first clockdomain in response to said dependent output clock; and second circuitryconfigured to operate in said second clock domain in response to saidreference clock and to receive said transfer enable signal, wherein saidtransfer enable signal allows synchronous, minimum latency informationtransfers between said first and second circuitry.
 12. The clockgenerator of claim 11, wherein J, K, M, and N are elected from a groupconsisting of 1, 2, 4, 6, 8, and
 10. 13. An apparatus for transferringdata with minimum latency between a first clock domain, a second clockdomain and a third clock domain, said apparatus comprising: a firstclock generator configured to generate a first dependent output clock; asecond clock generator configured to generate a second dependent outputclock; a main clock source configured to generate a reference clock forsaid first and second clock generators; gear ratio logic circuitryconfigured to receive said reference clock and said first and seconddependent output clocks, said gear ratio logic circuitry configured togenerate a first gear ratio output clock from said reference clock, saidfirst gear ratio output clock having a frequency being a first fraction,J/M, of the frequency of said reference clock, where J and M areintegers, said first and second clock generators receiving said firstgear ratio output clock as said reference-phase clock, said gear ratiologic circuitry configured to generate a second gear ratio output clockfrom said first dependent output clock, said second gear ratio outputclock having a frequency being a second fraction, K/N1, of the frequencyof said first dependent output clock, where K and N1 are integers, saidfirst clock generator receiving said second gear ratio output clock as adependent-phase clock, said gear ratio logic circuitry furtherconfigured to generate a third gear ratio output clock from said seconddependent output clock, said third gear ratio output clock having afrequency being a third fraction, L/N2, of the frequency of said seconddependent output clock, where L and N2 are integers, said second clockgenerator receiving said third gear ratio output clock as saiddependent-phase clock, said phase alignment circuitry in said firstclock generator phase-shifting said first dependent output clock suchthat the detected phase difference between said first and second gearratio output clocks is substantially zero, and the phase alignmentcircuitry in said second clock generator phase-shifting said seconddependent output clock such that the detected phase difference betweensaid first and third gear ratio output clocks is substantially zero;first circuitry operating in said first clock domain in response to saidreference clock, wherein said gear ratio logic circuitry is configuredto generate a first transfer enable signal based on said reference andfirst dependent output clocks, said first circuitry configured toreceive said first transfer enable signal; second circuitry operating insaid second clock domain in response to said first dependent outputclock, wherein said gear ratio logic circuitry is configured to generatea second transfer enable signal based on said reference and seconddependent output clocks, said second circuitry configured to receivesaid second transfer enable signal; and third circuitry operating insaid third clock domain in response to said second dependent outputclock.
 14. The apparatus of claim 8, wherein said clock generatorfurther includes a multiplexer coupled to said phase alignment circuitryand said frequency synthesis loop, said multiplexer configured toselectively disable said phase alignment circuitry.
 15. The apparatus ofclaim 8, wherein said frequency synthesis loop is further configured todivide said reference clock signal by a constant.
 16. The apparatus ofclaim 8, wherein said frequency synthesis loop is further configured tomultiply said reference clock signal by a constant.
 17. The apparatus ofclaim 8, wherein said clock generator further includes a switchingdevice coupled to one of said phase alignment circuitry and saidfrequency synthesis loop, said switching device configured toselectively disable said dependent output clock.
 18. The apparatus ofclaim 17, wherein said switching device further includes a multiplexercoupled to said phase alignment circuitry and said frequency synthesisloop, said multiplexer configured to selectively disable said phasealignment circuitry.
 19. The apparatus of claim 8 wherein said clockgenerator is incorporated inside said memory control unit.
 20. Anapparatus to receive a reference clock and a dependent clock fortransferring data between a first clock domain and a second clockdomain, said apparatus, comprising: first circuitry configured tooperate in a first clock domain in response to a reference clock; secondcircuitry configured to operate in a second clock domain in response toa dependent clock, said dependent clock having a frequency substantiallyequal to an integer ratio of a frequency of said reference clock andhaving a determined phase relationship with said reference clock; andgear ratio logic circuitry coupled to said first circuit and said secondcircuit, said gear ratio logic circuitry configured to receive saidreference and dependent clocks and to generate a transfer enable signalbased on said reference and dependent clocks, wherein said firstcircuitry is configured to receive said transfer enable signal and saidtransfer enable signal permits synchronous, minimum latency informationtransfers between said first circuitry and said second circuitry. 21.The apparatus of claim 20, wherein said first circuitry and said secondcircuitry are embedded in a memory control unit.
 22. The apparatus ofclaim 20, wherein said integer ratio is selected from a group consistingof 1/1, 2/3, 3/2, 3/4, 4/3, 3/5, 5/3, 4/6, 6/4, 6/8, 8/6, 6/10, and10/6.
 23. The apparatus of claim 21 further comprising in combination acentral processing unit, coupled to said memory control unit, saidcentral processing unit configured to operate in one of said first andsecond clock domains.
 24. The apparatus of claim 20, wherein a dependentclock generator adjusts the phase of said dependent clock in response tothe phase difference between said reference clock and said dependentclock.